Index of /sys/class/dma/dma0chan0/device/i2c_designware.0/iommu/subsystem/dmar1/devices/0000:00:04.0/power_limits/

../
power_limit_0_max_uw                               19-Oct-2026 17:24                4096
power_limit_0_min_uw                               19-Oct-2026 17:24                4096
power_limit_0_step_uw                              19-Oct-2026 17:24                4096
power_limit_0_tmax_us                              19-Oct-2026 17:24                4096
power_limit_0_tmin_us                              19-Oct-2026 17:24                4096
power_limit_1_max_uw                               19-Oct-2026 17:24                4096
power_limit_1_min_uw                               19-Oct-2026 17:24                4096
power_limit_1_step_uw                              19-Oct-2026 17:24                4096
power_limit_1_tmax_us                              19-Oct-2026 17:24                4096
power_limit_1_tmin_us                              19-Oct-2026 17:24                4096